Three dimensional (3D) memory devices are characterized by multiple layers, each of which can include a planar array of memory cells. For certain three-dimensionally stacked memory devices, active layers can comprise active strips of materials configured as bit lines or word lines for memory cells, stacked in spaced-apart ridge-like structures. The active layers can be made from a doped (p-type or n-type) or undoped semiconductor material. In such 3D memory, memory cells can be disposed at the cross-points of the stacked bit lines or word lines and the crossing word lines or bit lines, forming a 3D memory array.
Examples of memory devices like this are described in commonly owned U.S. Patent Publication No. 2012/0182806, filed Apr. 1, 2011, entitled Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures by inventors Shih-Hung Chen and Hang-Ting Lue and are also described in commonly owned U.S. Pat. No. 8,363,476, filed 19 Jan. 2011, entitled Memory Device, Manufacturing Method And Operating Method Of The Same, by inventors Hang-Ting Lue and Shi-Hung Chen, both of which are incorporated by reference as if fully set forth herein. In these examples, the active strips are coupled to pads on each layer. The pads are arranged in stairstep structures to provide landing areas for interlayer conductors. For large arrays in particular, the resistance of the pads can be relatively high, slowing down operation of the device. Also, the current paths to the individual active strips across the array can vary, making control circuitry and sensing circuitry more complex.